Section Article

Optimising the scheduling of Network-on-Chip switches to ensure Quality-of-Service and adapt hardware resources.
Author(s): Dr. Gajraj Sharma

Abstract
With the ongoing progress of nanotechnology the implementation of ultra-large-scale integration systems on chips (SoC) is becoming more feasible. The efficiency of System-on-Chips (SoCs) is progressively driving the performance of advanced applications especially in the realm of communication. A Network on Chip (NoC) is a system that is designed to provide an efficient and expandable system on chip. It incorporates ideas from distributed systems and computer networks to ensure organisation and scalability. These principles are used to establish connections between Intellectual Property (IP) cores. As the complexity of standard operating systems (SoC) increases it is getting increasingly challenging to meet real-time requirements. The topic of Network-on-Chip (NoC) research focusses on addressing global communication in System-on-Chip (SoC) architectures. This includes transitioning from a computation-centric approach to a communication-centric one. To build a real-time Network-on-Chip (NoC) it is essential to create components that exhibit predictability in terms of their computational memory and communication capabilities. The allocation and control of buffers in Network Interfaces (NIs) is often the decisive aspect in designing a Network-on-Chip (NoC) that meets certain requirements for data transfer rate and delivery time. The Quality of Service (QoS) in a network operating system (NoC) is primarily influenced by two key factors: the depth of the switching memory and the choice of packet scheduling algorithms. Subsequently it is crucial to configure these buffers to align with the network requirements and establish the right specifications before the design stages to ensure the desired performance in the NoC. The objective of this study is to analyse the performance of Network-on-Chip (NoC) systems that use mesh architecture in a specific domain. In order to evaluate the buffering demands in the NoC nodes several quality of service parameters such as drop computation delay and throughput will be analysed. Additionally it presents a new approach for arranging flights and showcases via a simulation research the enhancements achieved in many quality of service aspects.