Section Article

Optimising the Scheduling of Network-on-Chip Switches to Ensure Quality-of-Service and Adapt Hardware Resources
Author(s): Ram Gopal Yadav

Abstract
Network-on-Chip (NoC) has emerged as the foundational communication fabric in modern multi-core and many-core systems-on-chip providing scalable structured and high-bandwidth interconnects essential for parallel computing. As processing elements increase in number and diversity achieving predictable Quality-of-Service (QoS) and efficient hardware resource adaptation becomes critical to system stability latency guarantees and application performance. This research paper presents a comprehensive study of scheduling optimisation in NoC switches integrating architectural constraints multi-traffic contention service differentiation and dynamic resource adaptation. NoC switches serve as the routers responsible for packet forwarding virtual-channel allocation buffer management and flow control and their scheduling behaviour directly affects throughput latency fairness congestion mitigation and energy efficiency. Traditional fixed-priority or round-robin scheduling approaches are increasingly inadequate for heterogeneous workloads that exhibit time-varying traffic patterns memory-intensive behaviour and latency-sensitive interactions.