Section Article

Utilisation of a Very Large Scale Integration (VLSI) LNS Divider in Mobile 3D Graphics Processors
Author(s): Aarti Kaushik

Abstract
When it comes to 3D visual applications on mobile devices the need of having a low power consumption high throughput and compact chip space in the arithmetic unit outweighs the capacity to tolerate small errors. Amongst the several mathematical operations division is the most demanding and time-consuming. In order to develop and construct a divider using 0.25μm CMOS technology we use the logarithmic number system (LNS). By using a piecewise approximation method that integrates differential coefficients for logarithmic conversion it is feasible to enhance the precision of the outcome while concurrently minimising power consumption. When comparing our divider to the normal restoring divider we find that the operating speed is much improved however there is a little increase in the number of gates required. Furthermore we provide evidence that the error caused by our divider is less than the error caused by the LNS divider in the previous study.